%FILENAME%
vtr-9.0.0-1-riscv64.pkg.tar.zst

%NAME%
vtr

%BASE%
vtr

%VERSION%
9.0.0-1

%DESC%
Verilog to Routing -- Open Source CAD Flow for FPGA Research

%CSIZE%
7891605

%ISIZE%
22667235

%SHA256SUM%
033d2bac6bc904a17f135832068853263f7e26f1948fecc154bed209cb1bdd44

%URL%
https://verilogtorouting.org

%LICENSE%
MIT

%ARCH%
riscv64

%BUILDDATE%
1766429942

%PACKAGER%
Felix Yan <felixonmars@archlinux.org>

%DEPENDS%
ctags
tbb

%MAKEDEPENDS%
cmake
wget

